This invention relates to a clock reproducing circuit constituting technique for reproducing a clock timing component from a demodulated base-band signal, which is adapted to be used in a packet FSK (Frequency Shift Keying) signal receiver.
A first prior art method of extracting a clock signal component from a received signal consists of squaring a demodulated base-band signal, and then passing the squared signal through a band-pass filter in order to extract a clock signal component therefrom. The clock signal component is then passed from the band-pass filter, to an analog or digital PLL (Phase Locked Loop) circuit, in order to produce a clock signal. However, in this method, because it takes some time for the band-pass filter and the PLL circuit to respond, the clock signal is not produced on time when the packet signal is short. In order to produce a clock signal in a shorter period of time, a second prior art method has been used. This second method consists of immediately starting a digital PLL circuit when the base-band signal crosses "zero" (a bit synchronization signal positioned at a head portion of the packet). Thereafter, while the data section of the packet has switched to the next cycle, a clock signal is produced by squaring a base-band signal and then passing the squared signal to a band-pass filter (this second prior art method provides smaller jitter compared to the first prior art method). Within the first prior art method, it is preferred that there not be produced any bias distortion (DC offset) since the clock signal is produced directly from the base-band signal. Because this method requires that the frequency error at the time of transmission and reception be extremely small, a high precision oscillator must be used during transmission and reception. When the frequency error is very small, it is possible to correct the frequency by using an A.F.C. (Automatic Frequency Control) circuit without using a high precision oscillator. However, it has not been possible to eliminate the high precision oscillator, and therefore reduce the size and cost of the resulting apparatus, when the frequency error has been large. As mentioned, in the past, using a high-pass filter to eliminate such a large DC offset has not been possible because it has taken too long to generate a clock signal.
A bit synchronization signal (an information signal consisting of alternately repeated "O's" and "1's") is limited in frequency band during transmission. If the data transmission rate is 9600 bps, a base-band sine wave of 4800 Hz is produced. Using the base-band sine wave, it is possible to eliminate any DC offset using a high-pass filter, such as a differentiation circuit. However, a phase shifting occurs, and this phase shifting must be adjusted.
This can be expressed mathematically as follows. If the value of a DC offset (which is on the basis of a frequency error) is intended to be represented using the angular frequency of a sine wave (the bit synchronization signal), an input signal becomes following equation (1): ##EQU1## where s is Laplace transform operator. Since the transformer functions of a differentiating circuit and phase shifting circuit can be expressed by s/(s+c) and (s-d)/(s+d), respectively, an output signal O.sub.(s) becomes the following equation (2): ##EQU2## This can be developed to partial fractions, as following equation (3): ##EQU3## In the equation (3), A, B and C are residues which are found by the substitution of the radicals of the respective denominators, C is the conjugate of C, and j is an imaginary unit. The first and second terms of equation (3) represent respective transient terms while the third and fourth terms are steady-state terms which represent sine waves. Therefore, the third and fourth terms of equation (3) need not be considered in the instant case. The inverse transform O.sub.T(t) of the first and second, transient, terms can be calculated indirectly using the following inverse transform equation (4): EQU O.sub.T(t) =A.epsilon..sup.-ct +B.epsilon..sup.-dt .sub.-- (4)
In this equation (4), .epsilon. is the base of the naturalized logarithm. This exponential function is the above-mentioned transient, and in order that it can converge, the time is needed of about three times the respective reciprocal numbers of c and d, as is clear from the nature of an exponential function. Therefore, in order that the third and fourth, steady-state, terms (bit synchronization signal components) are available, the first and second transient, terms of the equation (3) must converge. This is the reason why prior art methods have required some time to generate a clock signal.